Heterogeneous Integration Technologies for AI System Scaling: Redefining Interconnects, Cooling and 3D Integration
The fields of advanced packaging and heterogeneous integration (APHI) have evolved at an unprecedented rate of innovation in recent years. This has been driven by two key driving factors: integrated circuit chiplets and AI compute needs. Together, these have driven the industry towards adopting package-level interconnect and bonding processes that are blurring the boundary between on-chip and off-chip interconnects, ever larger package substrates, 3D stacking, liquid cooling solutions, advanced power delivery architectures, and photonic I/Os. In this presentation, we will first review recent industry trends in APHI. Next, we will present our research in designing and fabricating passive-chiplets to build package functions that enable higher levels of integration density and performance, including cooling chiplets for 3D ICs that feature monolithic microfluidic cooling channels with high density through-silicon-vias, fiber-attach chiplets that self-align a bundle of fibers to a photonic integrated circuit at high precision, and mm-wave interconnect chiplets that provide broadband and low-loss connectivity for MMICs. Further, we will present advances in large area glass-core package substrates, including co-packaged optics. The schedule is as follows:
4-4.30 pm - Networking
4.30-6 pm - Lecture
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Prof. Muhannad Bakir
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4-4.30 pm - Networking
4.30-6 pm - Lecture