Technical Talk on "Analog Layout for High-Speed Circuits".

#layout #technology #device #ieeetechnicaltalks #integrated-circuits
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  Date and Time

  Location

  Hosts

  Registration


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  • Contact Event Host

  • Dr. Pritam Bhattacharjee

    pritam.bhattacharjee@vit.ac.in

    +918132863424, +919475009083

  • Co-sponsored by Vellore Institute of Technology, Chennai

  Speakers

SK of Mirafra Technology Private Limited

Topic:

Analog Layout for High-Speed Circuits

Biography:

Mr. Subhranil Kundu, is an Analog Layout Engineer with over three years of semiconductor industry experience. He holds an M.Tech in VLSI Design, and specializes in end-to-end physical design, precise floorplanning, and tapeout-ready analog layouts for complex and high speed blocks while mastering rigorous physical verification constraints.

Email:

Address:Mirafra Technology Private Limited, , Bengaluru, India, 560095




Agenda

This talk will explore key high-speed analog layout techniques for achieving performance, matching, and reliability. Topics include floorplanning, common-centroid, interdigitation, symmetry, dummy devices, multi-fingering, shielding, guard rings, substrate isolation, differential routing, critical-net routing, power and ground planning, parasitic minimization, IR-drop and electromigration control. The session also highlights challenges in advanced technology nodes, including process variation, reduced supply voltage, increased device density, and parasitic effects on high-speed analog circuit performance.