Code to Chip: Build & Accelerate with FPGAs
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#ieeeday2026
This session is proudly organized as part of the IEEE Day 2026 celebrations at the University of Peradeniya.
Join us for a hands-on workshop on hardware acceleration focusing on Xilinx FPGA boards. Professional skills covered include:
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Fundamentals of RTL and digital logic design
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FPGA synthesis and hardware acceleration
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Functional verification and performance analysis
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FPGA deployment and toolchain implementation
Date and Time
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- Faculty of Engineering
- University of Peradeniya
- Peradeniya, Sri Lanka
- Sri Lanka 20400
- Building: Drawing Office II
- Starts 10 October 2026 02:30 AM UTC
- Ends 14 October 2026 02:30 AM UTC
- No Admission Charge
Speakers
Mr. Kavinga Upul Ekanayake
Topic:
Build & Accelerate with FPGAs
Biography:
Head of Hardware Engineering, ACCELR
Chair-Elect, IEEE Sri Lanka Section