Tackling the Interconnect Scaling Bottleneck with Novel Conductors
Speaker:
Dr. Ching-Tzu Chen, IBM
Time:
October 16, 1pm-2pm
Online link:
Punchline:
Leveraging fundamentally new electronic structures, back-end-of-line (BEOL) interconnects with novel conductors can revert the rising resistivity in nanoscale wiring and overcome the BEOL performance scaling bottleneck.
Abstract:
Resistivity of conventional metals, such as Cu and Ru, increases sharply below 20 nm. Consequently, Cu interconnect scaling has become a key performance bottleneck in advanced-node integrated circuits. In this talk, we first introduce the fundamentals for the interconnect technologies and discuss the root cause of the scaling bottleneck. We then explore how the resistivity increase can be mitigated or even reverted by adopting novel conductors, namely, topological and anisotropic conductors. From theoretical simulations to hardware demos, we present the proof-of-concept verification of reversed resistivity scaling using topological Cosi nanowires at 8” wafer scale, showing that the predicted topological-surface-state physics can survive CMOS processing. We further survey the current research landscape and discuss the urgent need for high-throughput screening with examples. We will conclude with a list of requirements to help guide the search for best conductor candidates.
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- Lemont, Illinois
- United States