Computing Beyond Moore’s Law: From Heterogeneous Chiplets to 3D Adaptive Computing
Computing Beyond Moore’s Law: From Heterogeneous Chiplets to 3D Adaptive Computing
Speaker: Prof. Yu [Kevin] Cao, Dept. ECE, University of Minnesota
Abstract:
Enabled by advances in packaging technologies, the paradigm shift from monolithic integration to chiplet-based design is reshaping our computing systems, from data centers to edge AI. Composable chiplets offer scalable, flexible, and energy-efficient solutions for increasingly complex and heterogeneous workloads.
This talk presents our recent research on heterogeneous chiplet design and silicon prototypes. We first introduce HISIM, a simulation framework that integrates analytical models and machine-learning surrogates to evaluate power, temperature, performance, area, and cost (PTPAC) across diverse computing units, network topologies, and memory hierarchies. Building upon HISIM, we demonstrate a library of composable and reusable chiplets, integrated with neural architecture search to enable Pareto-optimal co-design of AI models and hardware architectures.
Beyond architectural optimization, we further introduce an emerging paradigm of 3D adaptive computing, leveraging dense vertical interconnects to enable massively parallel data movement and runtime hardware adaptation. By stacking distributed SRAM banks above reconfigurable processing elements, our 3D test chip in GF 22nm achieves sub-microsecond full-chip reconfiguration, over 1,000× faster than conventional FPGAs. This architecture combines ASIC-like efficiency with FPGA-like flexibility, opening new opportunities for SWaP-constrained applications in robotics, autonomous systems, and edge AI.
Bio: Yu Cao received the Ph.D. degree in electrical engineering from University of California, Berkeley, in 2002. He is now the Louis John Schnell Professor of Electrical and Computer Engineering at the University of Minnesota, Minneapolis, Minnesota. He has published numerous articles and three books on nano-CMOS modeling and physical design. His research interests include neural-inspired computing, hardware-algorithm co-design, and heterogeneous integration. Dr. Cao was a Distinguished Lecturer of the IEEE Circuits and Systems Society. He was a recipient of seven Best Paper Awards and Outstanding Researcher Awards from Intel, IBM, and others. He is a Fellow of the IEEE.
Date and Time
Location
Hosts
Registration
-
Add Event to Calendar
Loading virtual attendance info...
- Starts 26 October 2026 05:00 AM UTC
- Ends 20 November 2026 08:00 PM UTC
- No Admission Charge
Speakers
Prof. Yu [Kevin] Cao of University of Minnesota Twin Cities
Computing Beyond Moore’s Law: From Heterogeneous Chiplets to 3D Adaptive Computing
Enabled by advances in packaging technologies, the paradigm shift from monolithic integration to chiplet-based design is reshaping our computing systems, from data centers to edge AI. Composable chiplets offer scalable, flexible, and energy-efficient solutions for increasingly complex and heterogeneous workloads.
This talk presents our recent research on heterogeneous chiplet design and silicon prototypes. We first introduce HISIM, a simulation framework that integrates analytical models and machine-learning surrogates to evaluate power, temperature, performance, area, and cost (PTPAC) across diverse computing units, network topologies, and memory hierarchies. Building upon HISIM, we demonstrate a library of composable and reusable chiplets, integrated with neural architecture search to enable Pareto-optimal co-design of AI models and hardware architectures.
Beyond architectural optimization, we further introduce an emerging paradigm of 3D adaptive computing, leveraging dense vertical interconnects to enable massively parallel data movement and runtime hardware adaptation. By stacking distributed SRAM banks above reconfigurable processing elements, our 3D test chip in GF 22nm achieves sub-microsecond full-chip reconfiguration, over 1,000× faster than
conventional FPGAs. This architecture combines ASIC-like efficiency with FPGA-like flexibility, opening new opportunities for SWaP-constrained applications in robotics, autonomous systems, and edge AI.
Biography:
Yu Cao received the Ph.D. degree in electrical engineering from University of California, Berkeley, in 2002. He is now the Louis John Schnell Professor of Electrical and Computer Engineering at the University of Minnesota, Minneapolis, Minnesota. He has published numerous articles and three books on nano-CMOS modeling and physical design. His research interests include neural-inspired computing, hardware-algorithm co-design, and heterogeneous integration. Dr. Cao was a Distinguished Lecturer of the IEEE Circuits and Systems Society. He was a recipient of seven Best Paper Awards and Outstanding Researcher Awards from Intel, IBM, and others. He is a Fellow of the IEEE.
Email: