[Legacy Report] Burst Mode Power Efficient High Speed Receivers in CMOS

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High frequency jitter tracking in high
speed I/Os is beneficial for several
reasons including burst mode
functionality for power reduction.
However, providing such
high tracking
bandwidth in power and area efficient
way is challenging. In a clock forwarded
receiver the clock path in a 65nm CMOS
receiver comprises two
injection-locked
oscillators to frequency-multiply,
deskew, and track correlated jitter on a
pulsed clock forwarded from the
transmitter. Latency mismatch and data

rates are accommodated by controlling
jitter tracking up to 300MHz. Each
receiver consumes 0.92pJ/b at 7.4Gb/s
with a jitter tolerance of 1.5UI at
200MHz.
Similarly, in a clock embedded
receiver high frequency jitter can be
provided with a half rate injection
locked oscillator. The clock recovery
technique is verified with
experimental
results at 5-10 Gb/s 90 nm CMOS,
consuming 70 mW and acquiring lock
within 1.5 n

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