Advancements in ESD Protection Method and Modeling for High-Speed ICs
Abstract:
Failure of a high-speed integrated circuit (IC) resulting from an electrostatic discharge (ESD) event is one of the main reliability issues in many electronic products. The on-chip protection components are area intensive and costly, so they are typically made to protect against the smaller ESD events present during IC handling and not against the high-voltage ESD pulses present at the system-level.
In this webinar, we will review the main scenarios for ESD risks subjected to high-speed ICs. Then we will talk about the Transient voltage suppressor (TVS) diodes which are installed on high-speed I/O traces to improve system-level ESD protection. To protect the circuit, the majority of ESD current must flow into the external TVS diode rather than into the IC, but due to turn-on behavior, the TVS diode may not snap back when needed and the IC's internal protection may take most of the current. These race conditions between the internal and external ESD protection circuits will be discussed for a USB interface board. The results obtained from the measurements and by system efficient ESD design (SEED) simulations will be presented. This webinar discusses relevant ESD problems which take extensive precautions for ESD design engineers to become acquainted with them.
Date and Time
Location
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- Montreal, Quebec
- Canada H5A 1K6
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Énergie Matériaux Télécommunications (EMT) Research Centre
- Starts 21 November 2020 07:00 PM UTC
- Ends 01 December 2020 03:00 PM UTC
- No Admission Charge
Speakers
Dr. Javad Meiguni of Amazon Lab126
Biography:
Javad Meiguni, Ph.D. (IEEE Senior Member) received his M.S. and Ph.D. degrees in electrical engineering from the K. N. Toosi University of Technology, Tehran, Iran, in 2008 and 2013, respectively. He was an Assistant Professor with Semnan University, Faculty of Electrical and Computer Engineering, Semnan, Iran, until September 2017. He was with the Electromagnetic Compatibility (EMC) Laboratory, Missouri University of Science and Technology, Rolla, Missouri, USA, as a Visiting Assistant Research Professor from September 2017 until August 2019. He is currently an ESD System Design Engineer at Amazon Lab126, Sunnyvale, California, USA.
He has published near 50 technical papers in international journals and conferences, presented technical talks and training courses, and served as a member of the technical program committee and session chair. He serves as an active reviewer for some IEEE Transactions and Journals. His research interests include system-level ESD design, EMC, computational electromagnetics, and antenna.