Gs/s Analog-to-Digital Converters in sub-16nm Process Technologies
Many applications such as Digitally Modulated Radar (DMR), automotive ethernet, 5G, etc. require analog-to-digital converters (ADCs) with high-dynamic range as well as multi-GHz sample rates, and at the same time, the associated post-ADC signal processing requirements are driving the ADC implementations to sub-16nm process technologies. The challenges associated with implementing Gs/s ADCs in sub-16nm process technologies are significant and include: precise clocking, high-dynamic range with low supply voltages, Layout Dependent Effects (LDE), etc. Using Digitally Modulated Radar as the driving application, example ADC architectures that attempt to address these issues while taking best advantage of the sub-16nm process technologies will be presented. However, extensive research is still be needed to develop ADCs with the required performance at a reasonable cost and that also yield well, and industry and academia must cooperate and collaborate much more effectively in order to address this critical need.
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- San Diego, California
- United States
- Starts 04 March 2021 05:22 PM UTC
- Ends 17 March 2021 04:22 PM UTC
- No Admission Charge
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Dr. Doug Garrity
Gs/s Analog-to-Digital Converters in sub-16nm Process Technologies
Biography:
Doug Garrity (S’85-M’86-SM’04-F’11) received the B.S. degree from Portland State University, Portland OR, in 1986, the M.S. degree from the University of Idaho, Moscow, ID in 1993, and the Ph.D. degree from Arizona State University, Tempe, AZ in 2007 all in electrical engineering. He joined Motorola/Freescale/NXP in 1992 and is currently a Fellow of the Technical Staff at NXP, Chandler, AZ, where he is involved in the research and development of high-performance data converters for embedded applications. Dr. Garrity also teaches the graduate-level Nyquist-rate and Delta-Sigma analog-to-digital converter design classes at Arizona State University. He has received 47 U.S. Patents with several more pending in the field of data converter and analog VLSI circuits. Dr. Garrity became an NXP Fellow in 2015, was named a Freescale Fellow in 2010 and received Freescale’s Master Innovator Award in 2009. He was appointed a member of Motorola’s Science Advisory Board Associates, was a recipient of Motorola’s Distinguished Innovator Award, and was named a Motorola Dan Noble Fellow in 2003. Dr. Garrity also served as a member of the Technical Program Committee of the IEEE Custom Integrated Circuits Conference from 1994 through 2004. He also received the Semiconductor Research Corporation Mahboob Khan Outstanding Industry Liaison Award in 2001 and 2013. Dr. Garrity served as the chairman of the IEEE Kirchhoff Award committee in 2018 and 2019 and also served as the chairman of the SSCS Fellow Evaluation committee and has twice served as a guest editor for special issues of the IEEE Journal of Solid-State Circuits and served as an Associate Editor from 2002 to 2005. He has also served as an Associate Editor for the IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing.