Noise-Shaping SAR ADCs: From Discrete Time to Continuous Time

#silicon #SAR #ADC #NS-SAR

Noise-Shaping (NS) SAR ADCs become popular recently thanks to their low-power and high-resolution features. This presentation first summarizes and benchmarks different discrete-time (DT) NS-SAR implementations in literature. An open-loop duty-cycled residue amplifier is selected as a power-efficient solution to realize high residue gain. Then, a digital-predicted mismatch error shaping technique is introduced to improve the DAC linearity. The proposed DT NS-SAR ADC achieves 80 dB SNDR, 98 dB SFDR in a 31.25 kHz bandwidth while consuming 7.3 μW. Next, the NS-SAR architecture is extended from DT operation to continuous-time (CT) operation. The ADC sampling switch is removed and the loop filter is duty cycled to realize the CT NS-SAR operation. Compared to DT designs, the CT NS-SAR ADC is easy to drive and has inherent anti-aliasing function. As a proof of concept, the proposed CT NS-SAR ADC achieves 77 dB SNDR, 86 dB SFDR a 62.5 kHz bandwidth with a power consumption of 13.5 μW.

This talk will be held virtually. The talk will start with speaker introduction followd by a technical session. Afterwards, a QA session.