Co-Packaged Optics - Heterogeneous Integration of Photonic IC and Electronic IC
Silicon photonics are the semiconductor integration of EIC and PIC on a silicon substrate (wafer) with complementary metal-oxide semiconductor (CMOS) technology. On the other hand, co-packaged optics (CPO) are heterogeneous integration packaging methods to integrate the optical engine (OE) which consists of photonic ICs (PIC) and the electrical engine (EE) which consists of the electronic ICs (EIC) as well as the switch ASIC (application specific IC). The advantages of CPO are: (a) to reduce the length of the electrical interface between the OE/EE (or PIC/EIC) and the ASIC, (b) to reduce the energy required to drive the signal, and (c) to cut the latency which leads to better electrical performance. In the next few years, we will see more implementations of a higher level of heterogeneous integration of PIC and EIC, whether it is for performance, form factor, power consumption or cost. The content of this lecture is shown below.
Date and Time
Location
Hosts
Registration
- Date: 05 Mar 2024
- Time: 12:00 PM to 01:00 PM
- All times are (UTC-05:00) Indiana (East)
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- BRK 1001
- 1205 W State St
- West Lafayette, Indiana
- United States 47907
- Building: Birck Nano Technology Center
- Starts 19 February 2024 11:31 AM
- Ends 05 March 2024 11:31 AM
- All times are (UTC-05:00) Indiana (East)
- No Admission Charge
Speakers
Dr. John H. Lau of Unimicron Technology Corporation
Co-Packaged Optics - Heterogeneous Integration of Photonic IC and Electronic IC
Silicon photonics are the semiconductor integration of EIC and PIC on a silicon substrate (wafer) with complementary metal-oxide semiconductor (CMOS) technology. On the other hand, co-packaged optics (CPO) are heterogeneous integration packaging methods to integrate the optical engine (OE) which consists of photonic ICs (PIC) and the electrical engine (EE) which consists of the electronic ICs (EIC) as well as the switch ASIC (application specific IC). The advantages of CPO are: (a) to reduce the length of the electrical interface between the OE/EE (or PIC/EIC) and the ASIC, (b) to reduce the energy required to drive the signal, and (c) to cut the latency which leads to better electrical performance. In the next few years, we will see more implementations of a higher level of heterogeneous integration of PIC and EIC, whether it is for performance, form factor, power consumption or cost. The content of this lecture is shown below.
Silicon Photonics
Data Centers
Optical Transceivers
Optical Engine (OE) and Electrical Engine (EE)
OBO (on-board optics)
NPO (near-board optics)
CPO (co-packaged optics)
Integration of the PIC and EIC
2D Heterogeneous Integration of PIC and EIC
2D Heterogeneous Integration of ASIC Switch, PIC and EIC
2D Heterogeneous Integration of ASIC Switch, PIC and EIC with Bridges
3D Heterogeneous Integration of PIC and EIC
3D Heterogeneous Integration of ASIC Switch, PIC and EIC
3D Heterogeneous Integration of ASIC Switch, PIC and EIC with Bridges
Heterogeneous Integration of ASIC Switch, PIC and EIC on Glass Substrate
Summary
Biography:
Dr. John H Lau, with more than 40 years of R&D and manufacturing experience in semiconductor packaging, has published more than 530 peer-reviewed papers (385 are the principal investigator), 52 issued and pending US patents (31 are the principal inventor), and 23 textbooks (all are the first author). John is an elected IEEE fellow, IMAPS Fellow, and ASME Fellow and has been actively participating in industry/academy/society meetings/conferences to contribute, learn, and share.
