Rabia

This talk will introduce Cyber-Secure Biological Systems, leveraging living sensors constructed from engineered biological entities seamlessly integrated with solid-state circuits. This unique synergy harnesses the advantages of biology while incorporating the reliability and communication infrastructure of electronics, offering a unique solution to societal challenges in healthcare and environmental monitoring. In this talk, examples of Cyber-Secure Biological Systems, such as miniaturized ingestible bioelectronic capsules for gastrointestinal tract monitoring and hybrid microfluidic-bioelectronic systems for environmental monitoring, will be presented.

Additionally, I will introduce a universal noise-centric data decoding approach using GRAND that facilitates ultra-low-energy wireless communications, a critical requirement for the success of these biological systems and numerous other applications. In this talk, I will delve into the intricacies of interdisciplinary approach for system design, spotlighting the potential of energy-efficient integrated circuits in the domains of biosensing and wireless communications. These collaborative research projects involve MIT BE/MechE, BU ECE/BME, and MIT RLE-Northeastern University.

Biography:

Rabia Tugce Yazicigil is an Assistant Professor of ECE Department at Boston University and a Network Faculty at Sabanci University. She was a Postdoctoral Associate at MIT and received her Ph.D. degree from Columbia University in 2016. Her research interests lie at the interface of integrated circuits, bio-sensing, signal processing, security, and wireless communications to innovate system-level solutions for future energy constrained applications. She has received numerous awards, including the NSF CAREER Award (2024), Early Career Excellence in Research Award for the Boston University College of Engineering (2024), the Catalyst Foundation Award (2021), Boston University ENG Dean Catalyst Award (2021), and “Electrical Engineering Collaborative Research Award” for her Ph.D. research (2016). Dr. Yazicigil is an active member of the Solid-State Circuits Society (SSCS) Women-in-Circuits committee and is a member of the 2015 MIT EECS Rising Stars cohort. She was selected as an IEEE SSCS Distinguished Lecturer for the 2024-2026 term and elected to the IEEE SSCS AdCom as a Member-at-Large in 2024. She was selected as a member of the 2024 National Academy of Engineering (NAE) US Frontiers of Engineering (USFOE) cohort. She serves as an Associate Editor of the IEEE Transactions on Circuits and Systems-I (TCAS-I) and the IEEE Transactions on Circuits and Systems for Artificial Intelligence (TCASAI). Additionally, she is the Workshop Co-Chair of the IEEE ESSERC 2024, and a Technical Program Committee member of the IEEE ISSCC and RFIC.

Email:

Address:Ontario, Canada

Alvin

Despite the much debated end of Moore's Law, CMOS scaling still maintains economic relevance with 3nm finFET SoCs already in the marketplace for over a year and 2nm gate-all-around SoCs well into risk production. Modest feature size reduction and design/technology innovations co-optimized for primarily logic scaling continue to offer compelling node-to-node power, performance, area, and cost benefits. In this tutorial, we will start with a walk through memory lane, recounting a brief history of transistor evolution to motivate the migration from the planar MOSFET to the fully depleted FinFET. We will summarize the key process technology elements that have enabled the finFET CMOS nodes, highlighting the resulting device technology characteristics and challenges. This will set the context for motivating the introduction of the gate-all-around device architecture, namely nanoribbons or nanosheets, and unveiling the magic of how these devices are fabricated.

Biography:

Alvin Loke is a Senior Principal Engineer at Intel, San Diego, working on analog design/technology co-optimization for Angstrom-era CMOS. He has previously worked on CMOS nodes spanning 250nm to 2nm at Agilent, AMD, Qualcomm, TSMC, and NXP. He received his B.A.Sc. Eng. Physics from the University of British Columbia, and M.S. and Ph.D. E.E. from Stanford. He spent several years in CMOS process integration and has worked on analog/mixed-signal design focusing on a variety of wireline links, design/model/technology interface, and analog design methodologies. Alvin has been an active IEEE Solid-State Circuits Society (SSCS) volunteer since 2003, having served as Distinguished Lecturer, AdCom Member, CICC Committee Member, Webinar Chair, Denver and San Diego Chapter Chair, as well as JSSC, SSCL, and Solid-State Circuits Magazine Guest Editor. He currently serves as the VLSI Symposium Secretary and global SSCS Chapters Chair. Alvin has authored over 70 publications including the CICC 2018 Best Paper and invited short courses at ISSCC, VLSI Symposium, CICC, and BCICTS. He holds 29 US patents.

Email:

Address:Ontario, Canada