2025 IEEE EPS Phoenix Section Seminar: Challenges and Solutions for High-Speed Signaling in Future System-in-Packages by Kemal Aygun (Intel)

#high-speed #signaling #system-in-package #electronic-packaging
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Challenges and Solutions for High-Speed Signaling in Future System-in-Packages

Abstract:

With the rapid developments in artificial intelligence and other high performance computing applications, future electronic systems need to provide significantly improved performance. One area where the performance demand has been scaling very aggressively is for interconnecting different components and chiplets by means of system-in-packages with high-speed/high-bandwidth signaling. To address this demand, future system-in-package architectures and designs require innovations in package technologies, analysis and validation methods and tools, and standardization. This presentation will review some recent developments in advanced electronic packaging technologies that aim to provide significantly improved performance for both on- and off-package high-speed interconnects. It will also summarize some of the current challenges and solutions for the corresponding electrical methodologies and metrologies. Finally, recent progress on standardization of on-package high-speed signaling for seamless 2/2.5/3D integration of chiplets will be presented with some thoughts on future scaling and remaining challenges. 

Biography:

Kemal Aygün is a Fellow at Intel Foundry Technology Development organization, where he has been leading the development of high-bandwidth package and socket technologies and modeling and characterization methodologies for on- and off-package I/O interfaces. He has co-authored 5 book chapters, more than 100 journal and conference publications, and holds 180 patents. He was the General Chair of the 2020 IEEE Electrical Performance of Electronic Packaging and Systems Conference. Dr. Aygün is an IEEE Fellow and has been acting as a Distinguished Lecturer for the IEEE Electronics Packaging Society. He has a Ph.D. in Electrical and Computer Engineering from the University of Illinois at Urbana-Champaign.

Date: May 22, 2025

Location: Intel CH6 (5000 W Chandler Blvd, Chandler, AZ 85226, Google Maps)

Parking Instruction: 

  • Location Pin: https://maps.app.goo.gl/v7A23eB8gyjkZsbq9?g_st=com.google.maps.preview.copy
  • Please use the pin provided to enter the CH-6 building. Lobby is located at the entrance.
  • There is covered and uncovered parking available in front of this building accessible to visitors.
  • Visitor parking spots are clearly marked. Please use these designated visitor parking spots. The parking block in red would be the closest (Only few visitor spots available in Garage. None on 2nd floor).
  • More visitor parking is available in the lots which show green in the map below. (Safer option and more accessible).

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Registration at CH6 Lobby:

  • Registrants will be checked in prior arrival. Please identify yourselves and wait at the lobby, to be escorted to CH6-109 room

Agenda:
Refreshments: 4:00-4:30pm
Seminar Talk: 4:30-5:30pm


  Date and Time

  Location

  Hosts

  Registration


  • Date: 22 May 2025
  • Time: 11:00 PM UTC to 01:00 AM UTC
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  • 5000 W Chandler Blvd
  • Chandler, Arizona
  • United States 85226
  • Building: Intel CH6
  • Room Number: 109
  • Click here for Map
  • Contact Event Host

  • Christopher.J.Bailey@asu.edu

  • Starts 12 April 2025 07:00 AM UTC
  • Ends 22 May 2025 07:00 AM UTC
  • No Admission Charge




IEEE EPS Phoenix Section - Region 6: https://r6.ieee.org/phoenix-eps/