Gilson Wirth of Electrical Engineering, UFRGS, Brazil

Charge capture and emission by defects (traps) close to the Dielectric-Semiconductor interface is the major source of low-frequency noise in modern MOS devices. It also causes Bias Temperature Instability (BTI). The mechanisms involved in charge trapping are presented, including a critical discussion of key parameters such as trapping/de-trapping time constants and the amplitude of the fluctuations induced by single traps. A novel physics-based modeling and simulation approach for BTI, RTN and 1/f noise is presented. It allows for the derivation of analytical formulations for 1/f noise (frequency domain) and RTN (time domain) using a single modeling framework, where model parameters are the same in frequency and time domain.  Low Frequency Noise (and BTI) levels can vary by several orders of magnitude in deeply scaled devices, making variability a major concern in advanced MOS technologies. To ensure proper circuit design in this scenario, it is necessary to identify the fundamental mechanisms responsible for variability in noise and BTI. Time domain analysis is relevant for the analysis of digital and mixed-signal circuits.  In digital circuits, the RTN chronological statistics, especially trap occupancy switching, have direct impacts on circuit performance and reliability, as degradations like jitter of signals happen when a trap switches state. The area scaling of RTN induced jitter (phase noise) and its variability is detailed and discussed, aiming to support circuit designers in transistor sizing towards a more reliable design. The applicability of the model here presented to the evaluation of logic gates and circuits is demonstrated by case studies.

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Biography:

Gilson I Wirth (M’97–SM’07) received the B.S.E.E and M.Sc. degrees from UFRGS – Univ. Federal do Rio Grande do Sul, Brazil, in 1990 and 1994, respectively. In 1999 he received the Dr.-Ing. degree in Electrical Engineering from the University of Dortmund (TU Dortmund), Dortmund, Germany. He is currently a full professor at the Electrical Eng. Depart. at Univ. Federal do Rio Grande do Sul - UFRGS (since January 2007). From July 2002 to December 2006 he was professor and head of the Computer Engineering Department, Univ. Estadual do Rio Grande do Sul - UERGS. His current research work focuses on modeling and electrical simulation of charge trapping in the context of Bias Temperature Instability (BTI), Low-Frequency Noise (1/f and RTN) and Hot Carrier Degradation (HCD). He has also worked on ionizing radiation effects (TID and SET/SEU) on semiconductor devices. He focuses on collaborative work with academia and industry. He has established successful collaborative work with different companies and research groups in Europe, North and South America, and Asia. He is currently a Distinguished Lecturer of the IEEE Electron Devices Society. He also was a distinguished lecturer of the IEEE Circuits and Systems Society (term 2010-2011).

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