LOGICAL NEXUS

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Logical Nexus – A Smart Fusion of Fun, Teamwork, and Technology

The IEEE Circuits and Systems Society (CASS) and IEEE Signal Processing Society (SPS) Student Branch Chapters of Amrita Vishwa Vidyapeetham, Chennai Campus, in association with the Department of Electronics and Communication Engineering, successfully organized Logical Nexus – A Smart Fusion of Fun, Teamwork, and Technology on 14th October 2025 at the RHISC Lab.

With 33 teams and nearly 100 participants, the event provided a dynamic platform for students to combine creativity, technical skills, and collaboration. The competition was structured in three progressive phases—an IoT and Embedded Quiz, a Poster Design Round, and a Prototype Development stage—encouraging participants to move from theoretical knowledge to practical innovation.

The event concluded with the announcement of the top three teams:
1st Prize – Thadaladi
2nd Prize – Innova3
3rd Prize – CAScade

Logical Nexus 2025 proved to be an enriching experience, blending learning and innovation while promoting teamwork and hands-on problem-solving among aspiring engineers.

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• 337/1 A, Amrita Vishwa Vidyapeetham,Vallal RCK Nagar, SH 50A,
• Vengal, Tamil Nadu 601102
• Chennai, Tamil Nadu
• India 601102
• Building: Amrita Vishwa Vidyapeetham
• Room Number: RHISC Lab
• Click here for Map

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• Starts 10 October 2025 03:30 AM UTC
• Ends 13 October 2025 11:30 AM UTC
• No Admission Charge

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Agenda – Logical Nexus 2025
Date: 14th October 2025
Venue: RHISC Lab, Amrita Vishwa Vidyapeetham, Chennai Campus

9:00 AM – 9:30 AM – Registration and Inaugural Session

• Welcome Address

• Brief Overview of the Event and Rules

9:30 AM – 10:30 AM – Phase 1: IoT & Embedded Quiz

• Technical quiz to assess participants’ knowledge in IoT and Embedded Systems

• Segregated rounds for first-year and senior students

10:30 AM – 12:00 PM – Phase 2: Poster Design Round

• Qualified teams receive a problem statement

• Preparation and presentation of solution posters highlighting concept, system design, and feasibility

12:00 PM – 12:45 PM – Lunch Break

12:45 PM – 2:30 PM – Phase 3: Prototype Development

• Hands-on session to develop and demonstrate a working hardware prototype based on the proposed idea

2:30 PM – 3:00 PM – Evaluation and Results Announcement

• Judging of prototypes based on innovation, technical implementation, and problem-solving approach

• Announcement of winners and closing remarks

3:00 PM – Valedictory Session and Group Photo