The Past, Current, and Future of Dielectric [Breakdown] Research

#dielectrics #fabrication #application #device #dielectric-breakdown
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Presenter:  Dr. Ernest Y. Wu  IEEE Fellow  (formerly with IBM Research Division)

Abstract:

In this talk, we will give an overview of dielectric breakdown (BD) research with focus on industry’s needs and pursuit of fundamental understanding in this growing field. After a brief review of basic elements of dielectric properties, we will discuss critical reliability aspects of dielectrics for their sustainable lifetime in a wide range of applications. Various electrical transport characteristics and physical signatures of dielectric failures will be reviewed for a wide range of dielectric thickness from 35nm down to ∼ 1nm. We will describe different failure modes, so-called soft and hard BD modes as well as progressive BD modes which are relevant for accurate reliability forecast or prediction to maintain the industry scaling roadmap. We will provide an overview of several acceleration models used for reliability forecasts or lifetime projection. Besides attempts to form physics-based framework of dielectric breakdown, we will unravel statistical techniques and modeling approaches which are indispensable tools to characterize dielectric breakdown phenomena and establish our confidence in reliability forecast. We will highlight how dielectric BD, a failure mechanism for most applications, is employed as a fabrication tool to form a filament or filaments in resistive random-access memory (RRAM) devices for neuromorphic computing. Finally, we will address several fundamental roadblocks which will be the key areas for future research of dielectric breakdown.

 

 


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  • 94 University Place
  • Burlington, Vermont
  • United States 05405
  • Building: Lafayette Hall
  • Room Number: L111
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  • Starts 10 November 2025 02:40 PM UTC
  • Ends 19 November 2025 08:00 PM UTC
  • No Admission Charge

  Speakers

Ernest

Biography:

 Ernest Wu received his PhD in Physics from University of Kansas in 1989, after which he joined IBM. Over his 35 year career at IBM, Dr. Wu has been responsible for fundamental research and development of transistor reliability methodologies, especially in the area of dielectric breakdown. He has been involved in reliability qualification of technology nodes from 250nm to 2nm and is the chief architect and investigator for the development of the power-law acceleration model and time-dependent clustering breakdown model which have been widely adopted in microelectronics manufacturing. His most recent contribution to dielectric breakdown has led to the discovery of reversing a decades-long area-scaling law with wide application to AI neuromorphic devices such as resistive memory devices (ReRAM) as well as metal-insulator-metal capacitors (MIMCAP) used in CMOS technology.




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