Balaji

This talk will provide an overview of radiation effects in integrated circuits and discuss radiation
hardening techniques. The talk will focus on single-event effects (SEE) and will review the impact of
SEE in storage and combinational logic circuits. The semiconductor industry has been striving to keep up
with Moore’s law scaling predictions through innovative process solutions from planar to FinFET and to
current nanosheet processes. This has helped develop high-performance application specific integrated
circuits (ASIC) to suit a variety of space and terrestrial applications. On the other hand, with technology
scaling and the associated increase in packing densities and reduction in operating voltages, the critical
charge needed to cause single-event effects in digital circuits has decreased significantly resulting in
increased vulnerability to radiation. This talk will review hardening-by-design approaches used for
overcoming single-events in memories, latches and logic circuits. Error correction techniques for
memories along with spacial- and time- redundancy based approaches for latches and logic circuits will
be presented. Recent advancement in the radiation-tolerant design approaches that tradeoff performance
penalty with the extent of radiation tolerance to suit different applications will be discussed along with the
performance overhead vs. radiation tolerance comparisons. Finally, the talk will review scaling trends and
bias dependence of single-event upset rates from planar to FinFET processes with an emphasis on the
opportunities and challenges for radiation hardening in highly scaled technologies.

Biography:

Balaji Narasimham received his Ph.D. in electrical engineering from Vanderbilt University, Nashville,
TN, in 2008. He joined Broadcom, Irvine, CA in 2008 where he is currently a Master R&D Engineer and
leads the foundry reliability team. Dr. Narasimham’s work focusses on radiation effects and reliability of
semiconductor devices and circuits. He has been instrumental in developing design reliability and soft
error guidelines for Broadcom’s diverse products from planar to FinFET technologies enabling them to
achieve reliability targets at low performance overhead. His expertise enabled Broadcom secure product
designs in emerging satellite markets, where his guidance has been crucial in developing radiation-
hardened designs for specialized applications. He has authored or co-authored over 75 peer-reviewed
papers related to his research, has authored a book chapter on single-event transients and has three US
patents on efficient soft error mitigation. He has delivered invited talks and tutorials on radiation effects
topics at various conferences. His accolades include Outstanding Paper Awards at IEEE NSREC and
IEEE RADECS conferences and the Broadcom President’s Award for Excellence. He has served in the
technical program committees and chaired sessions at IEEE IRPS, IEEE NSREC and IEEE RADECS. He
also serves as a reviewer for various IEEE journals. He is a Senior Member of the IEEE.

Address:United States