UCL IEEE CASS Bootcamp — Designing Silicon from First Principles
A two-day hands-on introduction to integrated circuit design and the open-source tapeout workflow
This intensive two-day bootcamp brings together students, engineers, and enthusiasts from all backgrounds to explore the world of custom silicon design. No prior IC design experience is required.
Participants will be guided from the fundamentals of how transistors behave all the way through to the generation of a GDSII layout file ready for fabrication, following the same process used in Tiny Tapeout. Tiny tapeout is the open-source community shuttle program that has already sent hundreds of custom designs to a real chip foundry.
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- Sir Eric Ash Laboratory
- University College London
- London, England
- United Kingdom
- Building: Malet Place Engineering Building
- Starts 01 May 2026 11:00 PM UTC
- Ends 17 May 2026 11:00 PM UTC
- No Admission Charge
Agenda
Day 1: Circuits and HDL Introduction
The first day begins with an accessible introduction to IC design and the landscape of open-source tooling that has transformed what is possible outside of industry. Morning sessions cover transistor-level circuit design: how MOSFETs switch, how simple gates are constructed, and how basic analogue and digital building blocks are characterised through simulation. Attendees will work through guided workshop exercises using open-source SPICE-compatible tools, measuring key parameters and building intuition for the relationship between physical device behaviour and circuit performance.
The afternoon transitions to hardware description languages, where participants will write and simulate digital logic in HDL, learning how behavioural and structural descriptions translate into synthesizable circuits. Workshop exercises progress from simple combinational blocks through to small sequential designs, giving everyone practical experience with the design entry process used in modern digital flows.
Day 2: Workshops & ASIC workflow
Day two is dedicated to the complete ASIC flow. The morning sessions explain the Tiny Tapeout project in depth : how the shuttle model works, how individual designs are stitched into a shared die, and what happens between design submission and receiving a packaged chip. Attendees will then work through the full tapeout workflow hands-on: taking an HDL design through synthesis, floorplanning, place and route, design rule checking, and final GDS generation using the OpenLane flow. Each stage of the physical design process is explained in context, so participants leave understanding not just how to run the tools but why each step exists.
The day closes with a discussion of next steps: how to submit a design to an upcoming Tiny Tapeout shuttle, how to get involved with the broader open silicon community, and resources for continuing the journey into analogue design, custom standard cells, and beyond.