IEEE SWISS SSC TALKS (WEBINAR) / PhD Student Update / Low Power Oscillators
Dear Members,
We hope all of you are doing well and healthy.
Our Swiss Solid State Circuit Society is please to host Phd Student Update.
It's a program that aims to give the floor to local university students to present their work.
That work has been peer-reviewed and accepted in one of the main conferences of the SSC or CAS Society and has to do with circuits.
We think it is beneficial for >
1. Students can either have a mock presentation or try to engage locally and have more feedback.
2. Professional who gets aware of research done in Federal institutes or Engineering School.
3. Professor who may have interest to see what other labs are doing.
We start on November 26th with a Low power timer presented by Jiawei Liao, Doctoral Student at the at the Institute for Integrated Systems at the ETH Zürich.
The paper is going to be presented at VLSI2020 >
A 8.7ppm/°C, 694nW, One-Point Calibrated RC Oscillator using a Nonlinearity-Aware Dual Phase-Locked Loop and DSM-Controlled Frequency-Locked Loops
The video conferencing link will be provided on the day.
Please Join at 18:00 mute your headset or microphone.
We make a group picture in the begining for society report.
For the Q&A make sure to have your headset or a proper microphone.
The Agenda is as follow:
18:00 - 18:05 Welcome participants Teleconference set-up
18:05 - 18:25 Lecture By Jiawei Liao
18:25 - 18:40 Questions / Discussion
We look forward meeting you and having fruitful discussion.
Kind regards,
Mathieu Coustans for your IEEE Switzerland Solid State Circuit Society committee.
Date and Time
Location
Hosts
Registration
- Date: 26 Nov 2020
- Time: 06:00 PM to 06:45 PM
- All times are (UTC+01:00) Bern
-
Add Event to Calendar
- zurich, Switzerland
- Switzerland
- Starts 10 November 2020 01:00 AM
- Ends 26 November 2020 10:00 AM
- All times are (UTC+01:00) Bern
- No Admission Charge
Speakers
Jiawei Liao
A 8.7ppm/°C, 694nW, One-Point Calibrated RC Oscillator Using a Nonlinearity-Aware Dual Phase-Locked Loop and DSM ctr FLL
This presentation is about an on-chip timer composed of two DSM-controlled RC oscillators, locked through a non-linearity aware digital dual phase-locked loop. The proposed design achieves an accurate temperature coefficient below 8.7ppm/°C from 10 samples from two different wafer lots with only one-point calibration and an Allan deviation floor of 4 ppm. The power consumption is 694nW at 116 kHz.
Biography:
Jiawei Liao received the B.Eng. degree in electrical engineering from Huazhong
University of Science and Technology, China, and University of Birmingham, UK in
2016. He received M.Sc. degree in electrical engineering and information technology
from ETH Zurich, Switzerland, in 2018. He is currently pursuing a Ph.D. degree at the
Integrated System Laboratory, ETH Zurich. His current research interests include
digital and mixed-signal integrated circuit design, biosignal processing, and machine
learning.
Media
| sscs_swiss_2020 | 2.10 MiB |