Compact Modeling of GaN HEMTs for Power and RF Circuit Design

#RF #electronics #design #devices #HEMT

The IEEE EDS/SSCS Baltimore Chapter presents the IEEE Distinguished Lecturer Dr. Yogesh Chauhan, who will talk about the industry standard compact model for GaN based Power and RF circuit design.

Compact models are used by circuit designers using SPICE modeling tools to design analog or digital circuits for high-frequency and/or high-power circuits for many different applications.  The process of translating the device’s performance into an accurate model is an interesting and complex process.

If you are interested in learning more about the ASM-HEMT model for GaN HEMTs from its developer, please consider joining us for this insightful presentation.  


Gallium Nitride (GaN) High Electron Mobility Transistors (HEMTs) and their associated RF and power-electronic applications have been a topic of aggressive academic and industrial research over the past couple of decades. This is due to the commendable level of performance promised by the GaN material system and the hetero-junction that it forms with AlGaN, leading to features such as high breakdown voltage, high mobility, high saturation velocity, high sheet carrier density, the ability to withstand high operating temperatures etc. In order to take full advantage of these properties and to translate them into viable circuit applications a fully robust and accurate GaN HEMT model is of prime importance. In this talk, I will present our ASM-HEMT model for GaN-based power and RF devices. I will also briefly talk about our efforts in modeling of SiC based MOS transistors.



  Date and Time




  • Date: 05 Jun 2024
  • Time: 09:00 AM to 10:30 AM
  • All times are (UTC-04:00) Eastern Time (US & Canada)
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  • Event POC and Chapter Treasurer: Pankaj Shah

    • Chapter Chair: Paul Potyraj
    • Chapter Vice Chair: Richard Fu


  • Starts 16 May 2024 12:00 AM
  • Ends 05 June 2024 12:00 AM
  • All times are (UTC-04:00) Eastern Time (US & Canada)
  • No Admission Charge


Yogesh Singh Chauhan


Compact Modeling of GaN HEMTs for Power and RF Circuit Design


Yogesh Singh Chauhan is a professor at Indian Institute of Technology Kanpur, India. He was with ST Microelectronics during 2003-2004; Semiconductor Research & Development Center at IBM Bangalore during 2007 – 2010; Tokyo Institute of Technology in 2010; and University of California Berkeley during 2010-2012. He is the developer of several industry standard models: ASM-HEMT, BSIM-BULK (formerly BSIM6), BSIM-CMG, BSIM-IMG, BSIM4 and BSIM-SOI models. His research group is involved in developing compact models for GaN transistors, FinFET, Nanosheet/Gate-All-Around FETs, FDSOI transistors, Negative Capacitance FETs and 2D FETs. His research interests are RF characterization, modeling, and simulation of semiconductor devices.  

He is the Fellow of IEEE and Indian National Academy of Engineering. He is the Editor of IEEE Transactions on Electron Devices and Distinguished Lecturer of the IEEE Electron Devices Society. He is the chairperson of IEEE-EDS Compact Modeling Committee and IEEE Uttar Pradesh section. He has published more than 400 papers in international journals and conferences.


8:30 to 9:00 am Eastern Time,  sign in

9:00 to 10:00 am Eastern Time, Seminar

10:00 am to 10:30 am Eastern Time, Questions and discussions.


2024_Q2_DL_GaN-HEMT__1_-compressed 5.19 MiB