IEEE SWISS SSCS TALK : 55nm DDC Subthrehold MCU 2.5uA/MHZ by Marc Pons (Senior Engineer CSEM)

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Dear Colleagues,

CSEM stand with a long Experience in ultra-low-power digital implementation.
Since the 80's, and the pioneer work of CSEM, Technology did not stand still.
 
Today's FinFet, FDSOI, SOTB offers improved opportunities. This work exploit strong body factor of deeply-depleted channel CMOS at 0.5V to compensate frequency over PVT to ±6%, achieving 30x frequency and 20x leakage scaling in a 2.56uW/MHz RISC-Core with 3.13nW/kB 2.5uW/MHz SRAM. The whole system offer Frequency-leakage configurability implemented by current-controlled adaptive body bias at a fixed supply voltage.
 
The paper presented as of CICC 2019, set a World record for MCU Energy efficiency.
 
We look forward to hear from Marc.


  Date and Time

  Location

  Contact

  Registration



  • ETH Zurich IIS Departement
  • Gloriastrasse, 35
  • Zurich, Switzerland
  • Switzerland 8092
  • Building: ETZ Building Floor E
  • Room Number: E81
  • Starts 03 June 2019 10:00 PM
  • Ends 25 June 2019 05:00 PM
  • All times are Europe/Zurich
  • No Admission Charge
  • Register


  Speakers

Marc Pons
Marc Pons of CSEM SA

Topic:

55nm DDC Subthrehold MCU 2.5uA/MHZ

Biography:

Marc Pons received the M.S. (2005) and Ph.D. degrees (2012) in electrical engineering from the from UPC, in collaboration with the Intel Barcelona Research Center and CSEM SA on the topic of "Design for manufacturability and yield". From 2012 to 2014 he was Post-Doc at CSEM SA on the topic of Sub-Threshold design. Since 2014 to now he is a Senior R&D Engineer at CSEM SA, in the System-on-Chip, Integrated and Wireless Systems group. His research focus is related to low power SoCs.

Email:

Address:CSEM Headquarter, Rue Jaquet-Droz, 1, Neuchatel, Switzerland, Switzerland, 2000





  Media

Presentation This document include the onslide presentation of the seminar 3.25 MiB
Event report 774.05 KiB