State-of-the-Art Silicon Very Large Scale Integrated Circuits: Industrial Face of Nanotechnology

#Nanotechnology #VLSI #Technology #Si VLSI #and #a-Si #polysilicon #integrated #circuits #test #techniques.
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The Electron Devices Society, Northern Virginia/Washington Jt. Sections Chapter, in collaboration with the Nanotechnology Council, Northern Virginia/Washington Jt. Sections Chapter, is pleased to sponsor a Distinguished Lecturer Webinar by Dr. Michael Shur, Patricia W. and Sheldon Roberts Professor, Rensselaer Polytechnic Institute.


Ever since the proposal and demonstration of quantum dots in 1980 by Efros’ brothers and Dr. Ekimov, the relentless progress of nanotechnology has been unstoppable. And nowhere this progress is more evident as in the Si Very Large Scale Integrated Circuits (VLSI) technology. The minimum feature sizes of the Si VLSI reduced to 7 nm in 2017 with plans for the 5 nm and even 3 nm technology. With over 20 billion transistors on a square cm chip in 2018 and the expectations of reaching 1 trillion transistors on chip in the near future, the complexity of the VLSI
fabrication processes and the commensurate costs are overwhelming. The quality of the crystalline silicon becomes crucial to guarantee an acceptable yield, and the device physics involved is new and counter-intuitive. But industrial silicon nanotechnology is not limited to crystalline materials. Amorphous and polysilicon Thin Film Transistors fabricated on glass or even on cloth or paper enable integrated circuits with 50 nm tolerances over square meter sizes. These technologies have become disruptive with applications ranging from entertainment to communications dubbed 5G and Beyond 5G, to robotics and driverless cars, and to the new electronic and communication warfare. This talk will focus on the Computer Aided Design compact models required to support the design, characterization, and parameter extraction for Si VLSI and a-Si and polysilicon integrated circuits, and on the new patent pending VLSI test techniques needed to identify and diagnose bad or faked VLSI chips.



  Date and Time

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  • Date: 21 Jan 2021
  • Time: 12:00 PM to 01:00 PM
  • All times are (GMT-05:00) US/Eastern
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  • Co-sponsored by Baltimore Section Jt Chapter, ED15/SSC37
  • Starts 15 December 2020 12:00 PM
  • Ends 20 January 2021 07:00 PM
  • All times are (GMT-05:00) US/Eastern
  • No Admission Charge


  Speakers

Prof. Michael Shur of Rensselaer Polytechnic Institute

Topic:

State-of-the-Art Silicon Very Large Scale Integrated Circuits: Industrial Face of Nanotechnology

Ever since the proposal and demonstration of quantum dots in 1980 by Efros’ brothers and Dr. Ekimov, the relentless progress of nanotechnology has been unstoppable. And nowhere this progress is more evident as in the Si Very Large Scale Integrated Circuits (VLSI) technology. The minimum feature sizes of the Si VLSI reduced to 7 nm in 2017 with plans for the 5 nm and even 3 nm technology. With over 20 billion transistors on a square cm chip in 2018 and the expectations of reaching 1 trillion transistors on chip in the near future, the complexity of the VLSI fabrication processes and the commensurate costs are overwhelming. The quality of the crystalline silicon becomes crucial to guarantee an acceptable yield, and the device physics involved is new and counter-intuitive. But industrial silicon nanotechnology is not limited to crystalline materials. Amorphous and polysilicon Thin Film Transistors fabricated on glass or even on cloth or paper enable integrated circuits with 50 nm tolerances over square meter sizes. These technologies have become disruptive with applications ranging from 
entertainment, to communications dubbed 5G and Beyond 5G, to robotics and driverless cars, and to the new electronic and communication warfare. This talk will focus on the Computer Aided Design compact models required to support the design, characterization, and parameter extraction for Si VLSI and a-Si and polysilicon integrated circuits, and on the new patent pending VLSI test techniques needed to identify and diagnose bad or faked VLSI chips.

Biography:

Michael Shur

Patricia W. and C. Sheldon Roberts Professor of Solid State Electronics

Michael S. Shur received MSEE Degree (with honors) from St. Petersburg Electrotechnical Institute, and PhD. and Dr. Sc. Degrees from A. F. Ioffe Institute. He is Patricia and Sheldon Roberts Professor of Solid State Electronics and Professor of Physics, Applied Physics, and Astronomy at Rensselaer Polytechnic Institute and co-founder, President and CEO of Electronics of the Future, Inc. He was also a co-founder and Vice-President of Sensor Electronics Technology, Inc. (a leading producer of deep ultraviolet LEDs) and founder of co-founder of several other startups, including Electronics of the Future, Inc. Dr. Shur is Life Fellow of IEEE, APS, ECS, and SPIE, Fellow of the National Academy of Inventors, OSA, IET, MRS, WIF, and AAAS. Dr. Shur is Distinguished Lecturer of IEEE EDS society. His awards include St. Petersburg Technical University and University of Vilnius Honorary Doctorates, Distinguished Faculty Naval Research Fellowships, William H. Wiley 1866 Distinguished Faculty Award, Rensselaer Outstanding Engineering Professor Award, Institute of Electronic Technology Achievement Medal, ECS Electronic and Photonics Award, Jefferson Science Fellowship, Recognition Award from iNEER, Tibbetts Award for Technology Commercialization, IEEE Sensors Council Technical Achievement Award, IEEE Donald Fink Best Paper Award, IEEE Kirchmayer Award, the Gold Medal of the Russian Education Ministry, van der Ziel Award, Senior Humboldt Award, Pioneer Award, RPI Engineering Research Award, Wiley Award, RPI Outstanding Faculty Award, and several Best Paper Awards. Dr. Shur was listed by the Institute of Scientific Information as Highly Cited Researcher. His h-index is 111. In 2009, the Lithuanian Academy of Sciences elected him its Foreign Member.

Email:

Address:CII 6015 Rensselaer Polytechnic Institute 12180 USA, 110 8th Street, Troy, New York, United States, 12180





  Media

Link for the WebEx Recording of the Event Link for the WebEx Recording of the Event 11.96 KiB
Presentation Slides Presentation Slides 4.10 MiB