Landscape of Synaptic Weight Memories

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The Electron Devices Society (EDS), Northern Virginia/Washington Jt. Sections Chapters joined with The Nanotechology Council (NTC) are pleased to host an EDS Distinguished Lecture presented by Prof. Shimeng Yu, School of Electrical and Computer Engineering, Georgia Institute of Technology.

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Analog multilevel memories are the enabling device technologies for hardware acceleration of neuro-inspired computing workloads. In this lecture, we will survey the landscape of the emerging non-volatile memories that could serve the synaptic weights with a focus on resistive and ferroelectric devices. We will highlight the key device properties that are required for on-chip inference and/or training of deep neural network (DNN) models. We will use a multi-bit RRAM test vehicle to characterize the variability/reliability at array-level for inference. Then we will introduce an end-to-end benchmark framework DNN+NeuroSim to that is interfaced with PyTorch to evaluate versatile device technologies for DNN inference. Hybrid precision synapse that combines non-volatile memories with volatile capacitor is also presented to achieve in-situ training accuracy that is comparable with software. We will also showcase the integration of RRAM with peripheral CMOS at 40nm for a complete compute-in-memory prototype chip. Future research directions will be discussed. 



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  • Date: 11 Nov 2021
  • Time: 12:00 PM to 01:00 PM
  • All times are US/Eastern
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  • Virtual
  • United States
  • Starts 14 October 2021 05:34 PM
  • Ends 10 November 2021 05:30 PM
  • All times are US/Eastern
  • No Admission Charge


  Speakers

Prof. Shimeng Yu

Prof. Shimeng Yu of School of Electrical and Computer Engineering, Georgia Institute of Technology

Topic:

Landscape of Synaptic Weight Memories

Abstract: Analog multilevel memories are the enabling device technologies for hardware acceleration of neuro-inspired computing workloads. In this lecture, we will survey the landscape of the emerging non-volatile memories that could serve the synaptic weights with a focus on resistive and ferroelectric devices. We will highlight the key device properties that are required for on-chip inference and/or training of deep neural network (DNN) models. We will use a multi-bit RRAM test vehicle to characterize the variability/reliability at array-level for inference. Then we will introduce an end-to-end benchmark framework DNN+NeuroSim to that is interfaced with PyTorch to evaluate versatile device technologies for DNN inference. Hybrid precision synapse that combines non-volatile memories with volatile capacitor is also presented to achieve in-situ training accuracy that is comparable with software. We will also showcase the integration of RRAM with peripheral CMOS at 40nm for a complete compute-in-memory prototype chip. Future research directions will be discussed. 

Biography:

Bio:

Shimeng Yu is currently an associate professor of electrical and computer engineering at Georgia Institute of Technology. He received the B.S. degree in microelectronics from Peking University in 2009, and the M.S. degree and Ph.D. degree in electrical engineering from Stanford University in 2011 and 2013, respectively. From 2013 to 2018, he was an assistant professor at Arizona State University.

Prof. Yu’s research interests are the semiconductor devices and integrated circuits for energy-efficient computing systems. His research expertise is on the emerging non-volatile memories for applications such as deep learning accelerator, in-memory computing, 3D integration, and hardware security.

Among Prof. Yu’s honors, he was a recipient of NSF Faculty Early CAREER Award in 2016, IEEE Electron Devices Society (EDS) Early Career Award in 2017, ACM Special Interests Group on Design Automation (SIGDA) Outstanding New Faculty Award in 2018, Semiconductor Research Corporation (SRC) Young Faculty Award in 2019, and IEEE Circuits and Systems Society (CASS) Distinguished Lecturer, and IEEE Electron Devices Society (EDS) Distinguished Lecturer, etc.

Prof. Yu has served many premier conferences as technical program committee, including IEEE International Electron Devices Meeting (IEDM), IEEE Symposium on VLSI Technology, IEEE International Reliability Physics Symposium (IRPS), ACM/IEEE Design Automation Conference (DAC), ACM/IEEE Design, Automation & Test in Europe (DATE), ACM/IEEE International Conference on Computer-Aided-Design (ICCAD), etc.  He is a senior member of the IEEE.

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