IEEE SWISS SSC DISTINGUISHED LECTURE (WEBINAR) / ESD Design in High Voltage Smart Power Technologies


Dear Members,

We hope all of you are doing well and healthy,

Your Swiss Solid State Circuit Society chapter is please to host Lorenzo CERATI, Who is a Senior Member of the Technical Staff at ST Microelectronics.

The video conferencing link will be provided on the day to registred attendees.

The topic of the lecture is : " ESD Design in High Voltage Smart Power Technologies "

Please Join at 10:00 AM [CET] mute your headset or microphone.

We make a group picture in the begining for society report.

For the Q&A make sure to have your headset or a proper microphone.

The Agenda is as follow:

10:00 - 10:05 Welcome participants Teleconference set-up

10:05 - 11:15 Lecture

11:15 - 11:30 Questions / Discussion

We look forward meeting you and having fruitful discussion.

Kind regards,

Mathieu Coustans

For your IEEE Switzerland Solid State Circuit Society committee.

  Date and Time




  • Date: 25 Nov 2021
  • Time: 10:00 AM to 11:30 AM
  • All times are (UTC+01:00) Bern
  • Add_To_Calendar_icon Add Event to Calendar

Zoom Link will be provided

  • Starts 05 November 2021 01:00 AM
  • Ends 25 November 2021 09:00 PM
  • All times are (UTC+01:00) Bern
  • No Admission Charge


Lorenzo CERATI Lorenzo CERATI


ESD Design in High Voltage Smart Power Technologies

ESD design in High Voltage Smart Power is a very challenging task due to the peculiarities of these technology nodes. After a short introduction describing the status of the international standards and norms for the various application fields where these technologies are adopted, an overview of the process options and the typical device portfolios in the Smart Power world will be given. Different ESD protection concepts will be introduced, analyzing advantages and disadvantages of the various possible approaches to implement ESD networks (diodes, snapback, active clamps…). Finally, some examples of HV-technology and design-related challenges regarding ESD protections will be discussed, with a focus on parasitic bipolar formation and their impact on device performance.


Principal Engineer and senior member of the Technical Staff at STMicroelectronics. I received his M.Sc. degree in telecommunication engineering at the "Politecnico di Milano" Technical University in 1998, discussing a thesis on a CdZnTe cross-connect for optical networks. Since 2000, I have been working in STMicroelectronics in the ESD protections development team for Smart power technologies and now I am manager of the group responsible for ESD protections development, Latch-up immunity and bipolar parasitic analysis in BCD processes. I am also in charge of design teams support to define, implement and debug complex ESD architectures in BCD ICs.
I represent STMicroelectronics in the ESDA standardization committees and I am member of JWG HBM, JWG CDM, WG5.4, WG 5.5 (acting as vice-chairman), WG 5.6, and WG 14. Starting from 2016 I have been serving as member of the Technical and Advisory Support Committee (TAS).
I served multiple times as a member of the ESREF, ICICDT, IRPS, IEW, and EOS/ESD Symposium Technical Program Committees and authored several papers on ESD and EDA topics. Since 2015, I am member of the EOS/ESD symposium steering committee and I was General Chair at the 2020 EOS/ESD symposium. I am member of the ESDA Board of Directors’ since 2015.




IEEE_Lecture_ESD_Cerati_25Nov21 1.19 MiB
Introductory_slides_Nov2021 Introductory_slides_Nov2021 351.94 KiB